1. Field of the Invention
The invention relates to a semiconductor device with a passivation film. More particularly, the invention relates to a semiconductor device with a passivation film provided on a surface thereof, said passivation film comprising a SiON layer in contact with the surface of said semiconductor device, and a Si3N4 layer provided at the outer side of said SiON layer.
2. Description of the Related Art
A plurality of insulating thin films are superposed as a passivation film on a surface of a semiconductor device using a substrate composed of GaAs and the like for various purposes. Prior art technologies on such a passivation film, which is background of the present invention, are disclosed in, for example, Japanese Patent Publication No. 2-8455 and Japanese Patent Laid-Open Nos. 3-225828 and 3-268430.
Japanese Patent Publication No. 2-8455 discloses a structure of a passivation film comprising laminating a plurality of Si3N4 layers on a GaAs substrate (first prior art technology). Japanese Patent Laid-Open No. 3-225828 discloses a structure of a passivation film comprising laminating a plurality of SiON layers on a GaAs substrate (second prior art technology). Japanese Patent Laid-Open No 3-268430 discloses a structure comprising a SiON inner layer beside a GaAs substrate and a Si3N4 outer layer (third prior art technology).
However, the above-mentioned first to third prior art technologies, involve the following problems.
In the first prior art technology, although the passivation film has sufficient moisture resistance because the laminated Si3N4 layer will barely be permeated by water, the passivation film will lift off during thermal cycles of an environmental test or peel off during a wire bonding process because the bonding strength between GaAs and Si3N4 is relatively low. The passivation film having a laminate structure using a Si3N4 layer therefore does not have high reliability.
The second prior art technology does not cause the above-mentioned problems, i.e., lifting and peeling because a stress-free SiON passivation film having a high bonding strength to GaAs can be readily obtained. The passivation film having a laminate structure using a SiON layer, however, does not have satisfactory moisture resistance due to high water permeability inherent in SiON and does not have high reliability in this regard.
The third prior art technology is conceivable from the above-mentioned results, in which, in a passivation film having a laminate structure, a SiON layer having a high bonding strength to GaAs is formed at the inner side beside the GaAs substrate and a Si3N4 layer having high moisture resistance is formed at the outer side. However, mere modification of the passivation film, such as the third prior art technology, does not always assure satisfactory performance as described below in detail.
Although the SiON layer formed at the inner side, beside the GaAs substrate, improves the bonding strength with GaAs, the outermost layer must be a Si3N4 layer and a structure in which the periphery of the SiON layer is exposed must be avoided since SiON has essentially inferior moisture resistance. However, the periphery of the inner SiON layer at the edge of the passivation film is unavoidably exposed during lamination of the SiON layer and the Si3N4 layer and etching of a bonding pad section or scribe line. A sample having an exposed SiON layer periphery was subjected to, for example, a PCT test at 121xc2x0 C. and 85% RH for 100 hours in an unsaturated vapor atmosphere, and observed by optical microscopy. Discoloration and water penetration at the periphery of the SiON layer were observed.
Further, there are the following additional problems to be solved in the third prior art technology.
When IC is formed, for example, an etching process for making a resist pattern is extensively used because a thin film resistor is formed on the SiON layer of the semiconductor device. In this case, wet or dry etching on SiON is necessary. However, the limitations on the process conditions becomes severe because the etching rate of SiON is larger than Si3N4.
When two (a first and a second) SiON layers are formed on the GaAs substrate in order to use the second SiON layer as a material of a MIM capacitor in forming IC, the area of the capacity electrode must be larger than that formed on a Si3N4 layer because the relative dielectric constant of SiON is 5 or less while that of Si3N4 is 7 or more. This causes an increase in cost and severe process conditions for making the MIM capacitor on the second SiON layer. Even if the above severe process conditions are achieved, the thickness of the SiON layer becomes too great if the structure of the third prior art technology is applied. In view of a reliability of moisture resistance, a thin SiON layer is preferable.
It is an object of the present invention to provide a semiconductor device with a passivation film, which can solve the above-mentioned problems.
The invention provides a semiconductor device with a passivation film of the above mentioned kind, which is characterized in that the passivation film has an outermost layer of Si3N4, and the outermost layer has a portion being in contact with said semiconductor device. Said semiconductor device may have a bonding pad section formed by removing a part of said passivation film by etching, and said outermost layer covers the periphery of said bonding pad section or a scribe line.
The invention further provides a method of manufacturing the above semiconductor device, comprising the steps of 1) forming said SiON layer in contact with the surface of said semiconductor device, and 2) forming said outermost layer of Si3N4 on said SiON layer so as to be in contact with said semiconductor device.
The invention further provides a method of manufacturing the above semiconductor device, comprising the steps of 1) forming said SiON layer in contact with the surface of said semiconductor device, 2) forming said bonding pad section or said scribe line by removing a part of said SiON by etching, 3) forming said outermost layer of Si3N4 on said SiON and said bonding pad section or said scribe line, and 4) removing said outermost layer at said bonding pad section by etching so that said outermost layer at the periphery of said bonding pad section remains.
In accordance with the present invention as described above, since the portion of the passivation film in contact with the semiconductor device is composed of SiON having a high bonding strength, the bonding strength of the passivation film to the semiconductor device is increased, defects of the passivation film, such as lifting due to heat cycles and peeling during wire bonding, can be suppressed, and highly reliable semiconductive devices can be produced.
Since the passivation film has an outermost layer of Si3N4, and the outermost layer has a portion in contact with said semiconductor device, the passivation film is entirely covered with Si3N4 and has highly reliable moisture resistance. As a result, the effect of preventing penetrating water is improved.
Further, the invention provides a structure having a increased bonding strength between the semiconductor device and the passivation film with high moisture resistance, causing no limitation in the process of making an IC with introduction of a thin film resistor/MIM capacitor.
When the semiconductor device has a bonding pad section or a scribe line formed by removing a part of the passivation film by etching and the outermost layer covers the periphery of the bonding pad section and the scribe line, the SiON layer is not exposed even at the periphery of the bonding pad section and the scribe line. Thus, the penetration of water from there can be prevented.
Another aspect of the invention provides a semiconductor device with a passivation film of the above mentioned kind, which is characterized in that the exposed area of said SiON layer is nitrided.
In the above semiconductor device, the outermost layer of said passivation film may preferably be said Si3N4 layer.
In the above semiconductor device, said passivation film may have a structure consisting of a single SiON layer and a single Si3N4 layer.
In the above semiconductor device, the nitrided area of said SiON layer may be a plasma treated area by using gaseous ammonia.
The invention further provides a method of manufacturing the above semiconductor, comprising the steps of 1) forming said SiON layer in contact with the surface of said semiconductor device, 2) forming said Si3N4 layer above said SiON layer, and 3) nitriding the exposed area of said SiON layer which is not covered by said Si3N4 layer.
In accordance with the another aspect of the invention as described above, since the portion of the passivation film in contact with the semiconductor device is also composed of SiON having a high bonding strength, the bonding strength of the passivation film to the semiconductor device is increased, defects of the passivation film, such as lifting due to heat cycles and peeling during wire bonding, can be suppressed, and highly reliable semiconductive devices can be produced.
Since the passivation film is entirely covered with Si3N4, it has highly reliable moisture resistance, and it can enhance the effect of preventing penetration of water into the semiconductor device.
Also, in the present invention as described above, the compatibility of the increased bonding strength of the semiconductor device to the passivation film and the improved moisture resistance can be achieved by combining a SiON layer and a Si3N4 layer and by nitriding the exposed areas of SiON layer, without forming additional insulating layers for improving the moisture resistance. The passivation film having a laminate structure of only one SiON layer and only one Si3N4 layer is sufficiently effective for such a purpose. If such an advantage is not required, the passivation film may comprise two or more SiON layers and/or Si3N4 layers.
Since an ammonia plasma treatment of the SiON layer is capable of nitriding only the surface of the SiON layer, such an ammonia plasma treatment can be advantageously applied for nitriding the exposed peripheries of the SiON layer.
The invention will be described in detail by the following embodiments with the accompanying drawings.